Synchronous
Decade Counters

Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9 and then recycles to 0 again.  This is done by forcing the 1010 state back to the 0000 state.  This so called truncated sequence can be constructed by the following circuit.

From the sequence on the left, we notice that: Q0 toggles on each clock pulse. Q1 changes on the next clock pulse each time Q0=1 and Q3=0. Q2 changes on the next clock pulse each time Q0=Q1=1. Q3 changes on the next clock pulse each time Q0=1, Q1=1 and Q2=1 (count 7), or when Q0=1 and Q3=1 (count 9).

These characteristics are implemented with the AND/OR logic connected as shown in the logic diagram above.