Example 1.2

This example is taken from D. D. Gajski, Principles of Digital Design, Prentice Hall, 1997, p.234.

Example 1.2

Derive the next state, the output table and the state diagram for the sequential circuit shown in Figure 10.

Figure 10. Logic schematic of a sequential circuit.

SOLUTION:

The input combinational logic in Figure 10 is the same as in Example 1.1, so the excitation and the next-state equations will be the same as in Example 1.1.

Excitation equations:

D0 = CntQ0 = Cnt'*Q0 + Cnt*Q0'

D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'

Next-state equations:

Q0(next) = D0 = Cnt'*Q0 + Cnt*Q0'

Q1(next) = D0 = Cnt'*Q1 + Cnt*Q1'*Q0 + Cnt*Q1*Q0'

In addition, however, we have computed the output equation.

Output equation: Y = Q1Q0

As this equation shows, the output Y will equal to 1 when the counter is in state Q1Q0 = 11, and it will stay 1 as long as the counter stays in that state.

Next-state and output table:

Present State

Q1 Q0

Next State

Cnt=0

Cnt=1

Output

0 0

0 1

1 0

1 1

0 0	0 1
0 1	1 0
1 0	1 1
1 1	0 0

State diagram:

Figure 11. State diagram of sequential circuit in Figure 10.

To see how the states move from one to another click on the image.

Timing diagram:

Figure 12. Timing diagram of sequential circuit in Figure 10.

Click on the image to see its timing behaviour.

Note that the counter will reach the state Q1Q0 = 11 only in the third clock cycle, so the output Y will equal 1 after Q0 changes to 1. Since counting is disabled in the third clock cycle, the counter will stay in the state Q1Q0 = 11 and Y will stay asserted in all succeeding clock cycles until counting is enabled again.